YunSDR Y390
Covering the frequency range of 75 MHz to 6 GHz
Real time bandwidth up to 200MHz
40G high-speed interface
Ready to use software toolkit out of the box
MATLAB, Python, C #, C/C++secondary development APIs
Open source GNU Radio environment
Open source 4G and 5G protocol stacks
High performance miniaturized SDR
In stock:
＞1, ready to ship in 2 workdays
Overview
Applications
· Wireless access
· Test and measurement
· Early warning/radar
· Cable TV access
· Other high-performance RF applications
Y390 integrates the high bandwidth RF transceiver and high-performance Zynq SoC FPGA required for broadband wireless communication, which can meet the bandwidth requirements of most current wireless communication systems. The RF front-end adopts ADRV9009 transceiver, providing up to 200 MHz instantaneous bandwidth per channel and covering the frequency range from 75MHz to 6 GHz.
Product Description
Main features and interfaces
· RF channel: 2TX/2RX, TDD
· Transmitting power P1dB: ≥13dBm
· Supported channels: 75MHz~6GHz
· Real time bandwidth: 200 MHz
· Intermediate frequency mode: 2-channel zero intermediate frequency
· Emission EVM:<1.5%
· Configurable sampling rate: 122.88125153.6MHz
· PL DDR3 SDRAM：1GB，PS DDR3 SDRAM：1GB
· Data processing unit: XILINX ZYNQ SoC 7Z100, built-in dual core ARM Cortex-A9 CPU 800 MHz
· SPF+port (1 Gigabit Ethernet, 10 Gigabit Ethernet, Aurora), QSFP28 port (40Gbps, Aurora)
· Data interface: Gigabit Ethernet/QSFP/10G SFP+/USB 2.0 OTG/TF card
· Synchronization interface: Supports external local oscillator input and external reference clock input/output
· Debugging interface: USB JTAG
· Power supply: 12V DC power supply, power 34W
· Dimensions: Width 151 x Depth 205 x Height 46.8mm (including foot pad 8.5mm)
· Weight: Approximately 1.2 Kg
The baseband processor provides a rich range of programmable FPGAs for real-time and low latency processing, as well as a dual core ARM Cortex-A9 processor. Users can deploy applications on pre installed Linux embedded operating systems or use high-speed data interfaces to form SDR systems with the host. Y390 has a flexible reference clock design architecture that supports external PPS, external clock reference, and GPS synchronization interfaces, which is helpful for the implementation of MIMO systems.
The accompanying software tools can achieve common wireless signal processing functions such as device self check, spectrum analysis, recording and playback, helping engineers quickly locate and solve wireless related problems. The device driver supports mainstream open source projects such as GNU Radio, as well as FPGA underlying development. Users can quickly verify prototypes and reliably deploy various SDR applications, such as 5G base stations, signal intelligence, and spectrum monitoring.
Product Information
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